As today�s hardware architecture becomes more and more complicated, it is getting harder to modify or improve the\nmicroarchitecture of a design in register transfer level (RTL). Consequently, traditional methods we have used to develop a design\nare not capable of coping with complex designs. In this paper, we suggest a way of designing complex digital logic circuits with a\nsoft and advanced type of SystemVerilog at an electronic system level.We apply the concept of design-and-reuse with a high level of\nabstraction to implement elliptic curve crypto-processor server farms.With the concept of the superior level of abstraction to the\nRTL used with the traditional HDL design, we successfully achieved the soft implementation of the crypto-processor server farms\nas well as robust test bench code with trivial effort in the same simulation environment. Otherwise, it could have required errorprone\nVerilog simulations for the hardware IPs and other time-consuming jobs such as C/SystemC verification for the software,\nsacrificing more time and effort. In the design of the elliptic curve cryptography processor engine, we propose a 3X faster GF(2m)\nserial multiplication architecture.
Loading....